The present invention relates generally to integrated circuits, and more specifically to synchronizing signals in integrated circuits.
In synchronous integrated circuits, the integrated circuit is clocked by an external clock signal and performs operations at predetermined times relative the rising and falling edges of the applied clock signal. Examples of synchronous integrated circuits include synchronous memory devices such as synchronous dynamic random access memories (SDRAMs), synchronous static random access memories (SSRAMs), and packetized memories like SLDRAMs, and include other types of integrated circuits as well, such as microprocessors. The timing of signals external to a synchronous memory device is determined by the external clock signal, and operations within the memory device typically must be synchronized to external operations. For example, data words must be placed on a data bus of the memory device in synchronism (i.e. edge aligned) with the external clock signal, enabling a memory controller to latch these data words at the proper times to successfully capture the data words. To properly output the data words, the memory device develops an internal clock signal in response to the external clock signal, and this internal clock signal is typically applied to output buffers contained in the memory device to thereby clock the data words onto the data bus at the proper times. The data words and the external clock signal must be synchronized to ensure the memory controller latches the data words at the proper times to successfully capture the data words.
In the present description, xe2x80x9cexternalxe2x80x9d is used to refer to signals and operations outside of the memory device and controller, while xe2x80x9cinternalxe2x80x9d refers to signals and operations within the memory device controller. Moreover, although the present description is directed to synchronous memory devices, the principles described herein are equally applicable to other types of synchronous integrated circuits.
To synchronize external and internal clock signals in modern synchronous memory devices, a number of different approaches have been considered and utilized, including delay-locked loops (DLLs), phased-locked loops (PLLs), and synchronous mirror delays (SMDs), as will be appreciated by those skilled in the art. As used herein, the term synchronized includes signals that are coincident and signals that have a desired delay relative to one another. FIG. 1 is a functional block diagram illustrating a conventional delay-locked loop 100 including a coarse variable delay line 102 that receives a clock buffer signal CLKBUF and generates a coarse delayed clock signal CDCLK in response to the clock buffer signal. The coarse variable delay line 102 controls a coarse variable delay CD of the CDCLK signal relative to the CLKBUF signal responsive to a coarse delay adjustment signal CDADJ. A fine variable delay line 103 receives the CDCLK signal and generates a delayed clock signal CLKDEL in response to the CDCLK signal, with the CLKDEL signal having a fine variable delay FD relative to the CDCLK signal. The fine variable delay line 103 controls the value of the fine variable delay FD in response to a fine delay adjustment signal FDADJ.
A feedback delay line 104 generates a feedback clock signal CLKFB in response to the CLKDEL signal, the feedback clock signal having a model delay D1+D2 relative to the CLKDEL signal. The D1 component of the model delay D1+D2 corresponds to a delay introduced by an input buffer 106 that generates the CLKBUF signal in response to an external clock signal CLK, while the D2 component of the model delay corresponds to a delay introduced by an output buffer 108 that generates a synchronized clock signal CLKSYNC in response to the CLKDEL signal. Although the input buffer 106 and output buffer 108 are illustrated as single components, each represents all components and the associated delay between the input and output of the delay-locked loop 100. The input buffer 106 thus represents the delay D1 of all components between an input that receives the CLK signal and the input to the variable delay line 102, and the output buffer 108 represents the delay D2 of all components between the output of the variable delay line and an output at which the CLKSYNC signal is developed.
The delay-locked loop 100 further includes a phase detector and controller 110 that receives the CLKFB and CLKBUF signals and generates the coarse delay adjustment signal CDADJ applied to the coarse variable delay line 102 and the fine delay adjustment signal FDADJ applied to the fine variable delay line 103 in response to the phase shift between the CLKFB and CLKBUF signals. One implementation of the phase detector and controller 110 is described in U.S. Pat. No. 5,946,244 to Manning (Manning), which is assigned to the assignee of the present patent application and which is incorporated herein by reference. The phase detector and controller 110 adjusts the coarse and fine variable delays CD, FD as a function of the detected phase between the CLKBUF and CLKFB signals to thereby control an overall variable delay VD of the delay-locked loop 100, where VD=CD+FD.
In operation, the phase detector and controller 110 detects the phase difference between the CLKBUF and CLKFB signals, and generates the CDADJ, FDADJ signals to adjust the variable delay VD of the CLKDEL signal until the phase difference between the CLKBUF and CLKFB signals is approximately zero. More specifically, as the variable delay VD of the CLKDEL signal is adjusted, the phase of the CLKFB signal from the feedback delay line 104 is adjusted until the CLKFB signal has approximately the same phase as the CLKBUF signal. When the delay-locked loop 100 has adjusted the variable delay VD to a value causing the phase shift between the CLKBUF and CLKFB signals to equal approximately zero, the delay-locked loop is said to be xe2x80x9clocked.xe2x80x9d When the delay-locked loop 100 is locked, the CLK and CLKSYNC signals are synchronized. This is true because when the phase shift between the CLKBUF and CLKFB signals is approximately zero (i.e., the delay-locked loop 100 is locked), the variable delay VD has a value of NTCKxe2x88x92(D1+D2) as indicated in FIG. 1, where N is an integer and TCK is the period of the CLK signal. When VD equals NTCKxe2x88x92(D1+D2), the total delay of the CLK signal through the input buffer 106, variable delay line 102, and output buffer 108 is D1+NTCKxe2x88x92(D1+D2)+D2, which equals NTCK. Thus, the CLKSYNC signal is delayed by NTCK relative to the CLK signal and the two signals are synchronized since the delay is an integer multiple of the period of the CLK signal. Referring back to the discussion of synchronous memory devices above, the CLK signal corresponds to the external clock signal and the CLKDEL signal corresponds to the internal clock signal.
In the delay-locked loop 100, the coarse and fine variable delay lines 102, 103 are typically formed from a number of serially-connected individual unit delay stages 112, 114 as illustrated, with individual unit delay stages being added or removed to adjust the variable delay CD, FD as required, as will be understood by those skilled in the art. Each unit delay stage 112 in the coarse variable delay line 102 introduces a coarse unit time delay TCD while each unit delay stage 114 in the fine variable delay line 103 introduces a fine unit time delay TFD, where TCD=Nxc3x97TFD for some integer N. Typically, the total number of unit delay stages in the fine variable delay line 103 is such that the fine delay FD has a maximum value that is just less than the value of a coarse unit time delay TCD. For example, if TCD=6xc3x97TFD then the fine variable delay line 103 may include 5 unit delay stages so the maximum value of the fine delay FD is 5TFD. The overall variable delay of the delay lines 102, 103 is VD=Pxc3x97TCD+Qxc3x97TFD, and is adjusted in increments of TCD by the coarse variable delay line and in smaller increments of TFD by the fine variable delay line. For example, to adjust the delay CD of the coarse variable delay line 102 the CLKBUF signal is alternately applied to an input I1-I3 of the serially-connected unit delay stages 112 responsive to the CDADJ signal. Similarly, to adjust the delay FD of the fine variable delay line 103 the CDCLK signal is alternately applied to an input I1-I6 of the serially-connected unit delay stages 114 responsive to the FDADJ signal.
After the delay-locked loop 100 is initially locked, the overall variable delay VD may need to be adjusted to compensate for variations in the applied CLK signal or variations in the operation of the input buffer 106 or delay lines 102, 103 as a function of applied supply voltage (not shown) or temperature. As long as the variations of the CLK signal and operation of the components 102, 103, 106 are relatively small, the overall variable delay VD may be adjusted by varying only the value of the fine delay FD, while the coarse delay CD remains unchanged. For relatively large voltage or temperature changes, however, the resulting variations in the CLK signal and operation of components 102, 103, 106 necessitate the adjustment of the coarse delay CD to once again lock the delay-locked loop 100.
In changing the coarse delay CD, the number of coarse unit delay stages 112 delaying the applied CLKBUF signal is varied by switching one of the unit delay stages into or out of the path of the CLKBUF signal. Such switching of coarse unit delays 112 into or out of the signal path of the CLKBUF signal can result in xe2x80x9cedge perturbationsxe2x80x9d or xe2x80x9cjittterxe2x80x9d of the edge of the CLKBUF signal propagating through the delay line 102, which can result in the delay-locked loop 100 no longer being locked, as will be appreciated by those skilled in the art. For example, assume TCD=200 ps and TFD=30 ps, and assume the fine delay FD of the fine variable delay line 103 is currently 180 ps. At this point, no more fine unit delay stages 114 can be added to increase the delay, so a coarse unit delay TCD is added to the coarse delay CD and the fine delay is reset to a value of 90 ps (i.e., input to 14 as show in FIG. 1). In making this adjustment, the net change in the overall variable delay VD is 200 ps added to the coarse delay CD and 90 ps subtracted from the fine delay FD for a net adjustment to the variable delay VD of 110 ps.
At high frequencies of the applied CLK signal, the period TCK of the CLK signal is small and a small net change of, for example, 110 ps in the overall delay VD can result in an edge perturbation causing the delay-locked loop 100 to lose its lock, as will be appreciated by those skilled in the art. When the delay-locked loop 100 is not locked, the generated CLKSYNC signal is not synchronized with the CLK signal, and thus timing failures may result in circuitry performing operation responsive to the CLKSYNC signal. Moreover, because the delay-locked loop 100 takes a relatively long to time to lock (e.g., approximately 200 cycles of the CLK signal), circuitry operating responsive to the CLKSYNC signal must wait a correspondingly long time before commencing operation again to ensure proper timing relative to the CLK signal.
There is a need for a delay-locked loop that locks an applied clock signal over a wide range of voltage, temperature, and other operating parameters that can affect the operation of the delay-locked loop.
According to one aspect of the present invention, a synchronization circuit includes a first phase-shifting path circuit that receives an input signal and generates a first phase-shifted signal responsive to the input signal. The first phase-shifted signal has a fine phase shift and a coarse phase shift relative to the input signal, and the first phase-shifting path circuit adjusts the coarse and fine phase shifts responsive to coarse and fine control signals, respectively. A second phase-shifting path circuit receives the input signal and generates a second phase-shifted signal responsive to the input signal. The second phase-shifted signal has a fine phase shift and a coarse phase shift relative to the input signal, and the second phase-shifting path circuit adjusts the coarse and fine phase shifts responsive to coarse and fine control signals, respectively. A selection circuit is coupled to the first and second phase-shifting path circuits and selects one of the first and second phase-shifted signals responsive to a selection signal and applies the selected signal on an output.
A control circuit receives the input signal and develops the selection signal to select one of the first and second phase-shifted signals. In response to a phase shift between the input signal and the selected phase-shifted signal, the control circuit applies the fine control signals to adjust the fine phase shift of the phase-shifting path circuit generating the selected phase-shifted signal and applies the fine and coarse control signals to adjust the fine and coarse phase shifts of the other phase-shifting path circuit. In response to the fine delay of the phase-shifting path circuit that is generating the selected phase-shifted signal having a threshold value, the control circuit develops the selection signal to select the other one of the phase-shifted signals.